The present invention generally relates to a method for locally and globally planarizing chemical vapor deposition (CVD) of SiO.sub.2 layers onto structured silicon substrates. More specifically, the invention is related to the deposition of planar SiO.sub.2 layers that serve as insulating layers between individual levels of a multi-layer wiring in VLSI semiconductor circuits.
At the end of a manufacturing process of microelectronic circuits, all active and passive circuit elements must be connected to one another with metallic interconnects that are usually composed of aluminum. The interconnects are thereby etched by a dry etching method from a layer that is initially applied surface-wide.
Due to increasingly smaller spacing of the individual elements--down to 0.3 .mu.m in a 64 Mbit memory generation--as a result of increasingly higher integration and further due to the necessity of connecting the elements to one another independently of their position on the semiconductor circuit, a wiring which is arranged in a plurality of levels wherein each level is above one another is being increasingly selected, particularly in logic chips. Due to this arrangement, however, the wiring levels must be separated from one another by introducing insulating layers therebetween, also referred to as dielectric interlayers.
As a consequence of the increasing complexity, the surface of each and every wiring level before the application of the insulating layers becomes increasingly more similar to a pronounced "mountain range". As a result, considerable problems arise in the deposition of the insulating layers and also in the following lithography (producing via holes). Planarization processes are, therefore, utilized in order to compensate for irregularities caused by the structures therebelow based on the SiO.sub.2 layer.
Two fundamental problem areas typically arise from planarization processes. First, as is generally known, every enhancement of the resolution required during the course of miniaturization is accompanied by a decreasing depth of field. A low depth of field causes problems at the very outset in submicrometer lithography. The depth of field, however, is further reduced by factors such as the irregularity of the wafer surface itself which arises to a substantial degree in multi-layer wiring. Height differences must, therefore, be completely compensated which arise due to the structuring of the metallization levels to the farthest-reaching extent, i.e. to achieve an optimally high degree of planarization.
Second, as a consequence of the arbitrary electrical contacting of the components to one another, interconnect spacings from the submicrometer range up to the millimeter range occur in the individual wiring levels. A planarization method that is only locally satisfactory, i.e. in regions less than or equal to 1.5 .mu.m, is inadequate given a spacing between two raised structures becoming greater than or equal to 20 .mu.m. The tendency increases when SiO.sub.2 deposited thereabove--as well as photoresist layers--do not completely cover this broad range. This increasing tendency, of course, results in a reduced degree of global planarization.
Consequently, difficulties arise during planarization of a dielectric. On the one hand, extremely small interconnect spacings must be filled to be free of voids such that interconnects leading thereover are not interrupted. Even given large interconnect spacings, height differences must, as well, be compensated for in a satisfactory manner in order to enable lithography for submicrometer interconnects for the wiring plane leading thereover.
D. Wiedmann et al., "Technologie Hochintegrierter Schaltungen", Springer-Verlag, 1988, Section 3.5.5, discloses, in general, planarization technology. Employment of a photoresist as a planarizing auxiliary layer is disclosed by Wiedmann et al. wherein a planar surface of the resist is transferred onto a SiO.sub.2 layer in a re-etching technique in an ideal case. Given standard layer thicknesses of the resist of approximately 2 .mu.m, the range of the photoresist planarization lies in the 10 .mu.m region. As a result, the undesired lowering again occurs given greater spacings between the raised structures. The global degree of planarization is also deteriorated. A method for planarization with spin-on glass (SOG) is, likewise, generally disclosed in Wiedmann et al. The planarization degree that can be achieved is comparable to that of photoresist.
More recent planarization methods that, for example, particularly employ low-viscosity lacquers or a chemical mechanical polishing (CMP) method are also less satisfactory especially during a switch to greater spacings of, for example, a few 100 .mu.m.
The above-described planarization methods are structure-dependent, i.e. spacing-dependent, and, therefore, only have a limited planarization range. An article by T. H. Daubenspeck et al., J. Electrochem. Sco., Vol. 138, No. 2 (1991) also discloses a method for producing completely planarized dielectrics. The method employs what are referred to as dummy structures for filling out extensive regions not covered by the metallization. The dummy structures have the same thickness as the metallization. In the known method, local level fluctuations that arise due to the etching of the dummy structures must be subsequently either planarized by photoresist or must be compensated by chemical-mechanical polishing. The artificial aluminum structures not actually used proceeding from the circuit also have the disadvantage that coupling capacitances arise. Over and above this, the method involves extremely great outlay and is generally only suitable for chips having regular structures.
The conceivable possibility of achieving planarization by employing a highly surface-controlled coating process is successful only by filling narrow structures, such as trenches and blind holes.
From the selection of the metallization material, such as aluminum or copper, the temperature range of the deposition process or, respectively, planarization process is limited to less than 450.degree. C. Traditional CVD deposition of a SiO.sub.2 layer with TEOS (tetra-ethyl-ortho-silicate) as an initial substance or precursor at approximately 700.degree. C. must, therefore, be modified. Since plasma-enhanced oxide layers are not considered due to their only average conformity, CVD methods have been developed wherein the deposition temperature is lowered by adding ozone. Since decomposition and chemical attack of the ozone occurs at the substrate surface, one also succeeds in filling up metallization gaps of less than 0.3 .mu.m width void-free with TEOS as the precursor in chemical vapor depositions implemented with atmospheric pressure. This process along with SOG planarization, which is limited given a minimum gap width of 0.8 .mu.m, are the only methods that can fill narrow gaps with spacings far down into the submicrometer range void-free and with a good, local degree of planarization. The planarization range, however, again amounts to only a few .mu.m.
Over and above this, in view of the general utility of ozone-activated chemical vapor deposition of SiO.sub.2 layers (see K. Fujino, Y. Nishimoto, N. Tokumasu and K. Maeda, VMIC Conf. Proc. 445, 1991), problems arise with the conformity and the surface quality due to the identified dependency of the deposition mechanism on the surface quality of the substrate. In addition, Fujino et al. found that higher deposition rates arise on Si than on thermal SiO.sub.2 given employment of TEOS and, to an even greater degree, given the compounds OMTC (octa-methyl-cyclo-tetra-siloxane) and HMDS (hexa-methyl-disiloxane) given high ozone concentrations (approximately 5%). In order to overcome the disturbing dependency on the surface quality, Fujino et al. propose a plasma treatment of the surfaces composed of thermal SiO.sub.2 in order to improve their surface quality and in order to increase the deposition rate on the modified layer and match it to that of Si.